This invention generally relates to analog-to-digital converters, and more particularly relates to two step subranging analog-to-digital converters using recirculation through a single low resolution flash analog-to-digital converter.
As is well known, the function of an analog-to-digital converter (ADC) is to convert an analog input signal V.sub.i into a corresponding digital output represented by a coded array of binary bit signals. One type of ADC typically used for high speed applications is a parallel or flash converter. A flash ADC generally employs 2.sup.n -1 analog comparators to implement the quantization function of an ADC. In particular, the comparators trip points are spaced one least significant bit (LSB) apart by a series resistor chain and a voltage reference. For a given analog input voltage V.sub.i, all comparators biased below the voltage turn on, and those biased above turn off. A decoder is typically used to convert the output of the comparators into binary from.
Although a flash ADC has an advantage in being very fast, the fact that 2.sup.n -1 comparators are generally required is a disadvantage where relatively high resolution is desired. For example, although only 15 comparators are generally required for a 4-bit converter, 255 comparators are generally required for an 8-bit converter. To overcome this disadvantage, higher resolution ADCs commonly use two or more stages. For example, with an 8-bit converter, the result of a first 4-bit conversion is converted back to analog using a 4-bit digital-to-analog converter (DAC), and then subtracted from the analog input. The resulting residue is then converted by a second flash ADC, and the two sets of data are accumulated in a 8-bit register. By such arrangement, the number of bits can be doubled by merely doubling the number of comparators.
Another prior art technique for further reducing the number of required comparators is described in U.S. Pat. No. 5,070,332. In this arrangement, only one flash ADC is used, and the residue is recirculated back through it. In particular, with reference to prior art FIG. 1, an analog input signal V.sub.i is held at node 10 by track & hold 12. During a first step or phase, the held analog input is fed to m-bit flash ADC 14 through switch 16 which is controlled by timing and control logic 18. Flash ADC 16 is a low resolution converter, and converts the analog signal into the upper or most significant bits (MSBs) of its digital value. The most significant bits are stored in logic 20, and also fed to m-bit DAC 22. DAC 22 reconverts the first step m-bit digital value into an analog value which is fed to subtractor 24 where it is subtracted from the held input analog signal V.sub.i. The difference or residue is then coupled to differential amplifier 26 where it is multiplied up to the corresponding level of the MSBs. At the commencement of the second step or phase, switch 16 is switched to feed the multiplied residue to m-bit flash ADC 14 to provide the lower or least significant bits (LSBs). The LSBs of the second step are then combined with the MSBs from the first step in logic 20 to produce a high resolution digital output. For example, 4 LSBs are combined with 4 MSBs to provide a digital value having 8-bit resolution.